The present invention relates to the packaging of microelectronic devices. More particularly, the invention relates the single level packaging of silicon wafer die on a substrate, such as a circuit board.
Conventional fabrication of a microelectronics package involves two levels of packaging. With reference to FIG. 1, at the first level an integrated circuit die 20 is mounted to a lead frame 5, usually by an adhesive. Bonding pads 26 on the die are connected by bonding wires 28 to respective terminals 30 on the lead frame 5. The lead frame 5 and die 20 are then encapsulated by cover 7 to protect the die 20 and the bonding wires 28. The encapsulated lead frame and die thus constitute a first level of packaging. The encapsulated die and lead frame are mounted to a printed circuit board to create the second level of packaging. The lead frame may be mounted to the printed circuit board by way of solder reflow techniques or through the use of a socket mounted to the printed circuit board which is designed to receive the leads of the lead frame.
Recently, die have been mounted directly to the printed circuit board, thus eliminating the lead frame and the first level of packaging. Mounting directly to the circuit board decreases the length of the various electrical conductors such as leads and bonding wires, thus increasing the speed at which the chip can operate. FIG. 2 shows a conventional die 20 mounted directly to the circuit board 10 and secured thereto by suitable means such as by an adhesive. The die 20 has a set of bonding pads 26 which are located on one surface of the die 20. As shown in FIG. 2, the die 20 may be mounted with the bonding pads 26 of the die facing away from the surface of the circuit board 10 to which the die 20 is mounted. This type of arrangement is commonly referred to as conventional chip-on-board (COB).
FIG. 3 shows a die 20xe2x80x2 mounted directly to a substrate, such as circuit board 10. The die 20xe2x80x2 has a set of bonding pads 26xe2x80x2 which are located on the bottom surface of the die 20xe2x80x2. As is shown in FIG. 3, the die 20xe2x80x2 may be mounted with the bonding pads 26xe2x80x2 of the die 20xe2x80x2 facing the surface of a substrate such as the printed circuit board 10xe2x80x2 to which the die 20xe2x80x2 is being mounted. This type of arrangement is commonly referred to as flip chip. It is customary to provide a layer of material, known as a glob 46 top over the die 20xe2x80x2 to hermetically seal the die 20xe2x80x2. The glob top 46 serves as a chemical insulator protecting the die 20xe2x80x2 from humidity, oxidation and other harmful elements. The glob top 46 also protects the die 20xe2x80x2 mechanically and relieves mechanical stress in the die 20xe2x80x2.
While recent changes in the fabrication of microelectronics packages have resulted in a decrease in package size, further decreases are desired. It is also desirable to shorten the bonding wire lengths used to electrically connect the die to the circuit board. Increased assembly yield and operational speed result from using shortened bonding wires. It is also desirable to minimize the thickness of the resulting microelectronics package. Package thickness is important in many space sensitive applications.
The invention of the present application stacks multiple die on top of one another. The stacked die may or may not be partially or fully recessed into a first recess formed in a first surface of a substrate, such as a circuit board. The first recess may have a stepped cross-section to accommodate die of various sizes.
An aperture may be formed in the first recess, extending through the substrate for allowing wire bonding to a second surface of the substrate. Thus, a first die which is spaced relatively interiorly of a second die may be wire bonded through the aperture to terminals located on the second surface of the substrate. The second die may be wire bonded to terminals located on the first surface of the substrate.
In another exemplary embodiment of the invention, a second recess is formed in the second surface of the substrate. The terminals are located within the recessed portion of the second surface.
Stacking multiple die on a single substrate will greatly increase the space available on the circuit board for the addition of other components. Mounting the die in a recess formed in the substrate will reduce the thickness of the resulting microelectronics package. Fabricating a set of terminals on a surface opposed to the surface on which the die is mounted can shorten the lengths of the bonding wires which connect the die to the substrate. Locating a set of terminals in a second recess formed in the second surface of the substrate will also reduce the thickness of the package and further shorten the length of the bonding wires.